1. Field of the Invention
The present invention relates to a digital image processing apparatus and, more specifically, it relates to a digital image processing apparatus arithmetically processing original image data to enable image data converting processes such as gradation correction, sharpening of image quality, and processes such as feature extraction from the image data.
2. Description of the Prior Art
A digital image processing apparatus comprises an image input circuit for inputting image data, an image output circuit for outputting image data, an image memory storing image data, and a hardware portion such as processing circuits for carrying out arithmetic processes on image data in order to realize desired image processing function, and the circuits included in the hardware portion must be set up at a prescribed operation state. In order to carry out different image processing functions successively, the setting of the operation states must be updated successively. Although the setting and updating of operation states are well controlled by the software processing, the proportion of the software controlling the hardware to the entire software for image processing becomes large, causing disadvantages such that the program becomes large, the program largely depends on the hardware, and so on. In addition, since program fetching is required in controlling hardware, high speed control of the hardware portion becomes difficult, and the control in synchronization with the operation timing characteristic of the hardware is difficult. In view of the foregoing, a control circuit for controlling the hardware portion has been provided between the host CPU governing the software processing and the hardware portion realizing actual image processing in the conventional image processing apparatus, wherein information for controlling each hardware portion is micro-programmed in the control circuit, the microprogram is stored in a microprogram memory, and when a microprogram is read in accordance with a processing request from the host CPU, necessary hardware control is carried out to realize a prescribed image processing function. According to this method, the hardware control portion included in the software of the host CPU is considerably reduced, the hardware dependency of the software can be decreased, and the hardware can be controlled at high speed. The control operation in synchronization with the operation timing of the hardware becomes possible by carrying out the reading of microprogram during that period in the operation cycle of the hardware in which image data are not treated.
Prior to the present invention, we have proposed a control method utilizing a microprogram which enables control in synchronization with the operation timing of the hardware, as described above. We have listed various micro instructions for controlling the reading flow of the microprogram as well as the effects U.S. Ser. No. 089,558 (filed on Aug. 26, 1987). More detailed description will be given in the following with reference to the figures.
FIG. 1 is a block diagram showing one example of the structure of a previously proposed digital image processing apparatus utilizing microprogram system. In the figure, the digital image processing apparatus comprises a host CPU 1, a control circuit 2, an image input circuit 3, an image memory 4, a processing circuit 5, an image output circuit 6, a host CPU bus 7 which is used by the host CPU 1 to access hardware in the memory space of itself, a control bus 8 which is used by the control circuit 2 to apply micro instructions to each of the circuits 3.about.6, and an image data bus 9 for transferring image data between each of the circuits 3.about.6 at high speed.
The main role of the host CPU is to interpret the commands applied by an operator, to control the hardware in accordance with an algorithm governing the flow of the whole processing circuits, and so on. Sometimes, it directly accesses the image memory 4 to execute, by software processing, the function which can not be realized by the processing circuit 5, accesses the processing circuit 5 to initialize a table memory and the like therein, and so on. The basic arithmetic processes are effected by the processing circuit 5 on image data on the image data bus 9. The image data to be processed are provided from the image input circuit 3, the image memory 4, and so on. The results of processing are outputted onto the image data bus 9 to be written in the image memory 4, or to be inputted to the image output circuit 6. When a hardware processing should be done utilizing the processing circuit 5 and the image data bus 9, the control operation such as designation of an image output device to the image data bus 9 and of the image input device from the image data bus 9, setting of the function of the processing circuit 5, and so on must be done prior to the processing.
The control circuit 2 comprises a microprogram memory therein, and outputs necessary microprogram on the microprogram memory to the control bus 8 at a prescribed timing in accordance with a processing request from the host CPU 1. Various micro instructions for designating image output device, for designating image input device, for setting the function of the processing circuit 5, and so on are included in the read micro program. Each of the circuits to be controlled decodes the micro instruction for the circuit, and is set at a desired state prior to the processing state.
FIG. 2 shows an example of the structure of the control circuit 2 shown in FIG. 1.
A microprogram memory 20 stores microprogram.
An address counter 21 generates a read address to be applied to the microprogram memory 20.
An address selector 22 selects either a read address outputted from the address counter 21 or a write address which is provided by the host CPU 1 in setting microprogram to the microprogram memory 20.
An end detection flag 23 detects the end of reading of the microprogram.
A host CPU command decoder 24 decodes various commands applied from the host CPU 1 to the control circuit 2 through the host CPU bus 7A.
A micro instruction decoder 25 decodes micro instructions for controlling reading of the microprogram.
An address count permitting signal generating circuit 26 controls permission/non-permission of counting operation of the counter 21.
A timing signal generating circuit 27 generates timing signals for realizing reading of the microprogram in synchronization with the operation timing of the circuit controlled.
A flag register 28 is set by the host CPU 1 with the output being one of the jump conditions of a conditional jump instruction.
A frame counter 29 is used in a loop counter and the like, with the state of the counter being one of the jump conditions.
The micro instruction read from the microprogram memory 20 comprises an address portion A and a data portion D. A data buffer DB0 informs the host CPU 1 through the host CPU bus 7D of the state of the end detection flag 23. Data buffers AB1 and DB1 provides write data when the host CPU 1 sets microprogram in the microprogram memory 20, data buffers AB2 and DB2 transmit the address portion A and the data portion D of the micro instruction read from the microprogram memory 20 to the control bus 8 (8A and 8D).
The host CPU command decoder 24 provides six decode output H1-H6. The decode output H1 is a flag set command of the flag register 28. The decode outputs H2 and H3 are commands both applied to the address count permitting signal generating circuit 26, H2 is a start command and H3 is an end command. The decode output H4 is a clear command for clearing the count value of the address counter 21. The decode output H5 is an end check command for reading the state of the end detection flag 23. The decode output H6 is an end detection flag reset command for resetting the end detection flag.
A timing signal generating circuit 27 generates two timing signals. The timing signal T1 is utilized by the address count permitting signal generating circuit 26 to define the period in which the micro instruction can be transmitted. The timing signal T2 is a clock signal for counting of the address counter 21.
The micro instruction decoder 25 provides fixed decode outputs M1.about.M6. The decode output M1 corresponds to the count down instruction of the frame counter 29; the decode output M2 corresponds to an initial value load instruction of the flag counter 29; the decode output M3 corresponds to a reset instruction of the flag register 28; the decode output M4 corresponds to a read interruption instruction (EOFR instruction) which interrupts the reading of the microprogram until the start of the next frame; the decode output M5 corresponds to a read end instruction (EXIT instruction) which ends the reading of the microprogram; and the decode output M6 corresponds to a jump instruction, respectively. The decode output M5 sets the end detection flag 23.
The output J1 of the frame counter 29 and the output J2 of the flag register 28 are used as jump condition for decoding the conditional jump instruction. The output J1 becomes active when the count value of the frame counter 29 is 0, while the output J2 becomes active when the flag register 28 is set.
The operation of the controlling circuit 2 shown in FIG. 2 will be described in the following with specific examples.